The Hyper Duel MiSTer FPGA core moves to version 1.1 and adds Magical Error wo Sagase

Released on July 19, 2026, the MiSTer FPGA core for the mecha shoot'em up Hyper Duel (Technosoft/Taito, 1993) already offered a faithful recreation of the original arcade board: an Imagetek I4220 video chip reimplemented in SystemVerilog, two cycle-accurate Motorola 68000 processors clocked at 10 MHz, full raster interrupt handling across all 261 scanlines, a precisely calibrated OKI M6295 audio clock, and a Yamaha YM2151 chip for music. All of it with two-player support, adjustable settings, and automatic high-score saving.

Just days later, the developer has already released version 1.1 of the core, available as a direct download on GitHub, adding support for Magical Error wo Sagase (Technosoft/Jaleco, 1994), a second game running on the same dual-68000, Imagetek I4220 hardware architecture. To install it, users can follow the official MiSTer wiki, which walks through the steps for adding a new core to a setup.

A rare case of shared arcade hardware

Hyper Duel and Magical Error wo Sagase actually share near-identical arcade hardware, a common practice at the time to cut development costs. According to the update's description, the new version keeps «the same verified video chip, CRTC display window, and rendering engine as Hyper Duel v1.0», confirming the technical kinship between the two titles and letting the core stay just as accurate for this second game.

Source: GenerationAmiga